1. Field of the Invention
The present invention is directed generally to radio frequency (RF) power amplifiers that are at risk of being damaged as a result of poor load impedances, and more particularly to systems and methods for protecting RF power amplifiers.
2. Description of the Related Art
Power amplifiers are used in RF transmitters to rebroadcast RF signals at high power levels. Because RF transmitters must accurately rebroadcast these signals, the power amplifiers within the transmitters must have high fidelity (e.g., the power amplifiers should maintain linear performance).
In practice, a power amplifier stage may use a variety of silicon die technologies. One example is a field effect transistor (FET) such as a lateral diffused metal-oxide-semiconductor (LDMOS) transistor. The gate of the transistor is typically coupled to an RF input waveform at a given fundamental frequency, which typically comprises an RF carrier modulated with information to be communicated over the air. The transistor then generates an amplified RF signal at its drain (or “output”), which creates a voltage response between the drain and source. The RF voltage response is a function of a drain current generated in the transistor and the transistor's load impedance, which is based on an output matching network. Generally, the RF voltage response comprises a spectral component at a fundamental frequency and spectral components at one or more harmonic frequencies.
In controlled-impedance systems, the load that is connected to a signal source will reflect some of the source power. To get full transfer of power to a “load” (e.g., an antenna) from an RF signal source, the load impedance should be equal to the source impedance, which in practice is normally 50Ω (ohms). If the load impedance is different from the source impedance, a portion of the transmitted power will be reflected back. The figure of merit which establishes the quality of the load is called Voltage Standing Wave Ratio (“VSWR”), which defines how much of the outgoing signal is reflected back. The reflection coefficient () of the load is defined by:=(ZL−ZS)/(ZL+ZS)where ZL=load impedance (i.e., the antenna) and ZS=source impedance (i.e., the transmitter). It is noted that ZL and ZS are complex values, so the expression for  is a complex value with a magnitude and phase angle. The value of  is a ratio of the reflected voltage and forward-going voltage (i.e., =Vreflected/Vforward). Negative values imply that a 180-degree phase reversal also occurs. From this equation, it is seen that load impedances greater or less than the source impedance (e.g., 50Ω) will reflect some voltage. The amount of voltage that is reflected can be quantified by determining the VSWR:||=(VSWR−1)/(VSWR+1)Note that because power (P) is equal to voltage (V) squared divided by impedance (Z) (i.e., P=(V2)/Z or V=(P*Z)0.5), the reflection coefficient () which defines reflected voltage is the square root of the reflection coefficient that defines reflected power. Therefore, for a perfect load-match (ZL=50Ω), no voltage is reflected, and thus no power is reflected. If the load impedance is infinite (e.g., an open-circuit), 100% of the power and voltage is reflected back.
It is important to also note that in complex modulation schemes, such as Eight-ary Differential Phase-Shift Keying (“D8PSK”), the signal amplitude is varying. Thus there is a peak power and a root mean square (RMS) power. While RMS values are of primary concern regarding power delivery to the load, peak power is important when designing a method to avoid damage caused by reflections. The ratio peak power to RMS power is typically 1.414 in constant envelope modulation systems. This ratio is often referred to as a “crest factor,” and may be expressed in decibels. A typical crest factor for D8PSK modulation is approximately 4 dB.
In practice, transmitter antennas are not a perfect load. For example, an acceptable load mismatch for an antenna used in a Controller Pilot Data Link Communications (CPDLC) application is VSWR equal to 2. A VSWR equal to 2 will reflect about 33% of the forward-going voltage. Thus, if a radio is tuned to deliver 15 Watts RMS power into a 50Ω load, which requires a peak voltage of 32.5 volts, then the peak reflected voltage will be 10.7 volts (33% of 32.5 volts). With 100% addition of the forward and reflected voltages, the peak voltage at the load would then be 43.2 volts (32.5+10.7 volts).
As discussed above, the power amplifier used for a high power RF transmitter application is typically a discrete device such as an LDMOS transistor. Such devices are at risk of permanent damage due to excessive reflected voltages. Thus, for damage prevention, the peak voltage at the power amplifier is the most important factor.
RF devices such as CPDLC transmitters are generally cascaded systems of complex impedances. PCB traces, directional couplers, lumped-element filters, impedance-match circuits, a feeder cable, and even the load itself, have finite phase lengths which depend not only on the reactive values of their impedances, but also on the RF carrier frequency. What this implies is that the peak voltage at the load created by the forward and reflected signals will experience a phase-shift between the antenna and the power amplifier, so that while worst-case at the antenna can be 43.2 volts, using the example above, the phase shift can make the cumulative voltage at the transistor be any value between 32.5+/−10.7 volts.
When designing an RF transmitter, the phase of the antenna and feeder cable is an unknown. As a result, the forward and reflected voltages will superimpose and create a “net” delivered power from the transmitter. This is a natural response of traditional open-loop systems that can be seen as a power “sag,” or excess power, compared to a desired power. However, in closed-loop systems (e.g., systems using Cartesian feedback), an RF transmitter will attempt to compensate and will force the power back to its set point (e.g., 15 watts). This can cause damaging voltage levels at the power amplifier when, unlike an open-loop condition that would result in a “sag,” the feedback loop forces the power back up and creates excessive voltage at the transistor.